1. Field of the Invention
The present invention relates to virtually addressed memory operations in a multiprocessor computer system and more specifically to the translation lookaside buffers in such a system.
2. Art Background
In a computer system it is quite common for a central processing unit ("CPU") to have a cache memory to speed up memory access operations to main memory of the computer system. The cache memory is smaller, but much faster than main memory. It is placed operationally between the CPU and main memory. During the execution of a software program, the cache memory stores the most frequently utilized instructions and data. Whenever the processor needs to access information from main memory, the processor examines the cache first before accessing main memory. A cache miss occurs if the processor cannot find instructions or data in the cache memory and is required to access the slower main memory. Thus, the cache memory reduces the average memory access time of the CPU. For further information on cache memories, please refer to Computer Architecture: A Quantitative Approach, by John L. Hennessy and David A. Patterson, (Morgan, Kaufman Publishers, Inc., 1990).
In present day computing technology it is common to have a process executing only in main memory ("physical memory") while a programmer or user perceives a much larger memory which is allocated on an external disk ("virtual memory"). Virtual memory allows for very effective multi-programming and relieves the user of the unnecessarily tight constraint of main memory. To address the virtual memory, many processors contain a translator to translate virtual addresses in virtual memory to physical addresses in physical memory, and a translation lookaside buffer ("TLB"), which caches recently generated virtual-physical address pairs. The TLBs are essential because they allow faster access to main memory by skipping the mapping process when the translation pairs already exist. A TLB entry is like a cache entry where a tag holds portions of the virtual address and a data portion typically holds a physical page frame number, protection field, used bit and dirty bit.
When a page mapping of virtual-to-physical addresses of a given process is swapped out or thrashed as the process requires, the mapping has to be disposed of. If not, the next process issuing a virtual address may end up getting the mapping from the previous process, as the virtual addresses are reused by each process. In a single processor computer system, a flush command is typically sent to the TLB to demap the target page.
In a multiprocessor computer system with shared memory, however, sending an individual flush command to a processor becomes an expensive task since each processor along the system bus may have a copy of that page. Although interrupts can be sent to the processors, as is typically done in a single processor system, issuing interrupts to all the processors involves getting control of the system bus and stopping each processor's execution. Further, the processors, upon receiving the interrupts, will have to issue the same flush command to their respective TLBs and reply the issuing processor after getting control of the system bus. As each process becomes more complicated and the number of processors increases, the system-wide interrupts are occurring most of the time, since each of the processors may be running a job and issuing flush commands to all the other processors throughout the system.